1. Technical Field
The present invention relates generally to microprocessor controlled circuits, and more specifically to watchdog timer circuits. Still more particularly, the present invention relates to an intelligent watchdog timer circuit design.
2. Description of the Related Art
The use of watchdog circuits to monitor the operation of and reset the microprocessors in the event of aberrant operation (e.g., program abnormal execution/termination or an operation within an infinite loop) is well known. The watchdog circuits provided the reset command necessary to ensure that the microprocessor returns to a known reference state after a failure, in order to resume a designated operation.
The watchdog circuit comprises a counter that receives a clock input as a count source and outputs an overflow signal when its count reaches a predetermined number. The overflow signal is supplied into a system reset terminal as a reset signal of the microcomputer. The counter is reset cyclically by the program, and the reset operation of counter by the program is carried out at a time when the count value of the counter does not overflow. Those skilled in the art are familiar with the occurrence of overflow conditions and the resulting reset of the counter and system (e.g., microprocessor) that occurs.
Conventional watchdog circuits are implemented around a delay element. This delay element is occasionally implemented using an RC circuit if the timing requirement is under a second. Typical watchdog circuits are implemented digitally and with precision, using a simple count-up (i.e., incremental) counter for its delay element. With this system configuration, the system must reset the counter before the counter overflows.
FIGS. 1 and 2 illustrate a conventional watchdog timer connected to a host system. As shown in FIG. 1, watchdog circuit 101 is coupled to host system 110 via two signal paths, watchdog overflow signal 108 and restart watchdog signal 106. Watchdog circuit 101 comprises counter 105, which receives a clock input from a known source such as a system clock (not shown).
FIG. 2 illustrates state diagram representations of watchdog circuit 101 and system 110. State diagram of watchdog circuit 101 includes five states, with a transition from states one through five based on inputs received from system 110. State one 202 represents the initial power on state at which the watchdog circuit initializes watchdog counter to zero (block 204). State two 206 represents a decision input of the clock time to the counter. From state two 206, the circuit moves to either state five 208 or to a delay element 212. The delay element 212 represents a single delay loop within/associated with state two 206 until the clock time changes.
At state five 208, the circuit determines whether a toggle signal was received/detected from the system. When a toggle signal is detected, the circuit returns to block 204 at which the watchdog counter is initialized to zero. If no signal is detected, the counter is incremented (block 210) and then the circuit passes to state three 214 at which the circuit determines whether the counter is at an overflow state. When the counter is not at an overflow state, control is returned to state two 206 via delay element 212. When an overflow condition is registered, control passes to state four 216 at which the system is reset. Also, at block 218, the system may either log the occurrence of the fault (overflow) before the watchdog function is reactivated or alternatively the system may decide not to enable the watchdog after the occurrence of the fault.
From the system perspective, only two states are relevant. At state one 220 a determination is made whether the time to toggle the watchdog has arrived. When the time to toggle the watchdog circuit has not arrived, control is returned to state one 220 via delay element 224. When the time to toggle the watchdog circuit has arrived, control passes to state two 222, at which the watchdog signal is pulsed.
A large number of watchdog timers are reset by simple transitions detected from their host system. For example, if a typical five minute watchdog timer sees any transition within the time-out period (i.e., five minutes), the watchdog timer will treat this transition as a valid keep-a-live signal from the host system and the watchdog timer will restart its timers/counter. One drawback to this approach however, is that in some faults, a hung system may produce sufficient random keep-a-live pulses that would keep the watchdog from performing its desired monitoring/signaling task.
Some improvements and other alternative designs of watchdog timers have been proposed. Included among these are:
U.S. Pat. No. 6,385,274 provides a watchdog circuit that prevents unexpected signals being created before the watchdog issues a reset. However, this patent does not prevent false refreshes;
U.S. Pat. No. 5,864,663 provides a watchdog circuit that issues an overflow signal that can be used as a reset signal for the system;
U.S. Pat. No. 5,099,153 describes a watchdog circuit that counts down until a condition is met; and
European patent 025163A2 provides a watchdog timer circuit that utilizes a charging/discharging capacitor as its timer instead of a counter with a clock input.
Notably, none of the above methods intelligently addresses the problem of false keep-alive pulses while a system is in a hung state. Again, random keep-a-live signals prevents the above conventional watchdog designs from reliably performing its required task. One approach to implement a more intelligent watchdog circuit requires the use of a small microcontroller, but this approach is expensive, and thus cost prohibitive. The present invention addresses the desirability of having a more intelligent but easier-to-implement solution for watchdog timers.